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| Features * Low-voltage and Standard-voltage Operation - 5.0 (VCC = 4.5V to 5.5V) - 2.7 (VCC = 2.7V to 5.5V) - 1.8 (VCC = 1.8V to 3.6V) Internally Organized 65,536 x 8 2-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility Write Protect Pin for Hardware and Software Data Protection 128-byte Page Write Mode (Partial Page Writes Allowed) Self-timed Write Cycle (5 ms Typical) High Reliability - Endurance: 100,000 Write Cycles - Data Retention: 40 Years - ESD Protection: >4000V Automotive Grade and Extended Temperature Devices Available 8-pin PDIP and 20-pin JEDEC SOIC, 8-pin LAP, and 8-ball dBGATM Packages * * * * * * * * * 2-wire Serial EEPROM 512K (65,536 x 8) * * AT24C512 Description The AT24C512 provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device's cascadable feature allows up to 4 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin PDIP, 20-pin JEDEC SOIC, 8-pin Leadless Array (LAP), and 8-ball dBGA packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions. Pin Configurations Pin Name A0 - A1 SDA SCL WP NC Function Address Inputs Serial Data Serial Clock Input Write Protect No Connect 20-pin SOIC A0 A1 NC NC NC NC NC NC NC GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC WP NC NC NC NC NC NC SCL SDA A0 A1 NC GND 8-pin PDIP 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-pin Leadless Array VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 NC GND Bottom View 8-ball dBGA VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 NC GND Rev. 1116D-07/00 Bottom View 1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Block Diagram Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with AT24C128/256. When the pins are hardwired, as many as four 512K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pins are not hardwired, the default A1 and A0 are zero. 2 WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write operation creates a software write protect function. Memory Organization AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128-bytes each. Random word addressing requires a 16-bit data word address. AT24C512 AT24C512 Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V. Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, TAC = 0C to +70C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current (1.8V option) Standby Current (2.7V option) Standby Current (5.0V option) Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level (1) Test Condition Min 1.8 2.7 4.5 Typ Max 3.6 5.5 5.5 Units V V V mA mA VCC = 5.0V VCC = 5.0V VCC = 1.8V VCC = 3.6V VCC = 2.7V VCC = 5.5V VCC = 4.5 - 5.5V VIN = VCC or VSS VOUT = VCC or VSS READ at 400 kHz WRITE at 400 kHz VIN = VCC or VSS 1.0 2.0 2.0 3.0 0.2 2.0 0.6 A A ISB2 ISB3 ILI ILO VIL VIH VOL2 VOL1 Note: 1. VIN = VCC or VSS VIN = VCC or VSS 0.10 0.05 -0.6 VCC x 0.7 6.0 6.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 A A A V V V V Output Low Level Output Low Level VCC = 3.0V VCC = 1.8V IOL = 2.1 mA IOL = 0.15 mA VIL min and VIH max are reference only and are not tested. 3 AC Characteristics Applicable over recommended operating range from TA = -40C to +85C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. 1.8-volt Symbol fSCL tLOW tHIGH tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance Notes: (1) 2.7-volt Min Max 400 1.3 1.0 5.0-volt Min Max 1000 0.6 0.4 Units kHz Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time Inputs Fall Time (1) Min Max 100 4.7 4.0 0.1 4.7 4.0 4.7 0 200 1.0 300 4.7 100 20 100K 4.5 s s 0.55 0.05 1.3 0.6 0.6 0 100 0.9 0.05 0.5 0.25 0.25 0 100 s s s s s ns 0.3 300 0.6 50 10 100K 100K 0.25 50 0.3 100 s ns (1) Stop Set-up Time Data Out Hold Time Write Cycle Time 5.0V, 25C, Page Mode s ns 10 ms Write Cycles 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3K (2.7V, 5V), 10K (1.8V) Input pulse voltages: 0.3VCC to 0.7VCC Input rise and fall times: 50ns Input and output timing reference voltages: 0.5VCC Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C512 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high. 4 AT24C512 AT24C512 Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O) Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O) (1) Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 5 Data Validity Start and Stop Definition Output Acknowledge 6 AT24C512 AT24C512 Device Addressing The 512K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all 2wire EEPROM devices. The 512K uses the two device address bits A1, A0 to allow as many as four devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. DATA SECURITY: The AT24C512 has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at VCC. data word address will "roll over" and previous data will be overwritten. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page, to the first byte of the first page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6). Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2). PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 127 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3). The data word address lower 7 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 128 data words are transmitted to the EEPROM, the 7 Figure 1. Device Address Figure 2. Byte Write Figure 3. Page Write Figure 4. Current Address Read 8 AT24C512 AT24C512 Figure 5. Random Read Figure 6. Sequential Read 9 Ordering Information tWR (max) (ms) 10 ICC (max) (A) 3000 ISB (max) (A) 6.0 fMAX (kHz) 1000 Ordering Code AT24C512C1-10CC AT24C512-10PC AT24C512-10UC AT24C512W1-10SC AT24C512C1-10CI AT24C512-10PI AT24C512-10UI AT24C512W1-10SI AT24C512C1-10CC-2.7 AT24C512-10PC-2.7 AT24C512-10UC-2.7 AT24C512W1-10SC-2.7 AT24C512C1-10CI-2.7 AT24C512-10PI-2.7 AT24C512-10UI-2.7 AT24C512W1-10SI-2.7 AT24C512C1-10CC-1.8 AT24C512-10PC-1.8 AT24C512-10UC-1.8 AT24C512W1-10SC-1.8 AT24C512C1-10CI-1.8 AT24C512-10PI-1.8 AT24C512-10UI-1.8 AT24C512W1-10SI-1.8 Package 8C1 8P3 8U3 20S 8C1 8P3 8U3 20S 8C1 8P3 8U3 20S 8C1 8P3 8U3 20S 8C1 8P3 8U3 20S 8C1 8P3 8U3 20S Operation Range Commercial (0C to 70C) 3000 6.0 1000 Industrial (-40C to 85C) 10 1500 0.6 400 Commercial (0C to 70C) 1500 0.6 400 Industrial (-40C to 85C) 10 800 0.2 100 Commercial (0C to 70C) 800 0.2 100 Industrial (-40C to 85C) Package Type 8C1 8P3 8U3 20S 8-lead, 0.300" Wide, Leadless Array Package (LAP) 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8-ball, die Ball Grid Array Package (dBGA) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options Blank -2.7 -1.8 Standard Operation (4.5V to 5.5V) Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 3.6V) 10 AT24C512 AT24C512 Packaging Information 8C1, 8-lead, 0.300" Wide, Leadless Array Package (LAP) Dimensions in Millimeters and (Inches)* 8P3, 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA .400 (10.16) .355 (9.02) PIN 1 .280 (7.11) .240 (6.10) .037 (.940) .027 (.690) TOP VIEW SIDE VIEW 5.10 (0.201) 4.90 (0.193) .300 (7.62) REF 8.10 (0.319) 7.90 (0.311) BOTTOM VIEW 1.32 (0.052) 1.22 (0.048) 8 7 4.76 (0.187) 4.66 (0.183) 6 5 0.34 (0.013) 0.24 (0.009) 1.22 (0.048) 1.12 (0.044) 1 2 3 4 0.92 (0.036) 0.82 (0.032) 0.95 (0.037) 0.85 (0.033) 1.14 (0.045) 0.94 (0.037) 0.38 (0.015) 0.30 (0.012) .210 (5.33) MAX SEATING PLANE .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .100 (2.54) BSC .015 (.380) MIN .022 (.559) .014 (.356) .325 (8.26) .300 (7.62) .012 (.305) .008 (.203) 0 REF 15 .430 (10.9) MAX * Controlling dimension: millimeters 8U3, 8-ball, die Ball Grid Array Package (dBGA) Dimensions in Millimeters and (Inches)* 20S, 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters) TOP VIEW 3.40 (0.134) 0.020 (0.508) 0.013 (0.330) 0.299 (7.60) 0.420 (10.7) 0.291 (7.39) 0.393 (9.98) PIN 1 5.21 (0.205) .050 (1.27) BSC SIDE VIEW BOTTOM VIEW 0.38 (0.015) 0.513 (13.0) 0.497 (12.6) 0.105 (2.67) 0.092 (2.34) 8 1 7 2 0.012 (0.305) 0.003 (0.076) 6 0.75 (0.029) 5 1.48 (0.058) 0.75 (0.029) 3 4 0 REF 8 0.013 (0.330) 0.009 (0.229) 1.33 (0.052) 0.52 (0.020) 0.035 (0.889) 0.015 (0.381) * Controlling dimension: millimeters 11 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Printed on recycled paper. 1116D-07/00/xM Terms and product names in this document may be trademarks of others. |
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